The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device which can reduce an external resistance of a gate and a method for fabricating the same.
As semiconductor devices are scaled down, channel resistance is reduced and threshold voltage is also decreased. Thus, a current gain may be resulted as the channel resistance decreases due to the reduced channel length with respect to operating current.
However, it has become difficult to secure a current gain through the reduced channel length as the scaling down of semiconductor devices continues to use nano technology. The difficulty occurred because a sub-threshold leakage current increases while the channel resistance decreases with the gate channel length being reduced.
In order to reduce the sub-threshold leakage current, a doping concentration level in a gate channel region is being increased. That is, a uniform level of a threshold voltage needs to be maintained as semiconductor devices are being scaled down where a crossing point between on/off states is obtained at the target threshold voltage. In other words, it is difficult to obtain an improved channel resistance with the reduced gate channel length that results in a current gain because the threshold voltage is also increased in order to reduce the leakage current.
Furthermore, a short channel effect may increase due to the reduced channel length, causing mobility degradation to worsen. Thus, the current may be reduced even if the channel length is decreased.